vishay siliconix dg721, dg722, dg723 document number: 66586 s11-1474-rev. e, 01-aug-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 1.8 v to 5.5 v, 4 ? dual spst switches description the dg721, dg722 and dg72 3 are precision dual spst switches designed to operate from single 1.8 v to 5.5 v power supply with low power dissipation. the dg721, dg722 and dg723 can switch both analog and digital signals within the power supply rail, and conduct well in both directions. fabricated with advance subm icron cmos process, these switches provide high precision low and flat on resistance, low leakage current, low parasitic capacitance, and low charge injection. the dg721, dg722 and dg723 contain two independent single pole single throw (spst) switches. switch-1 and switch-2 are normally open for the dg721 and normally closed for the dg722. for the dg723, switch-1 is normally open and switch-2 is normally closed with a break-before- make switching timing. the dg721, dg722 and dg723 are the ideal switches for use in low voltage instruments and healthcare devices, fitting the circuits of low voltage adc and dac, analog front end gain control, and signal path control. as a committed partner to the community and the environment, vishay siliconix manufactures this product with lead (pb)-free device termination. the tdfn8 package has a nickel-palladium-gold device termination and is represented by the lead (pb)-fr ee ?-e4? suffix to the ordering part number. the msop-8 package has tin device termination and is represented by ?-e3?. both device terminations meet all jedec standards for reflow and msl rating. as a further sign of vishay siliconix's commitment, the dg721, dg722 and d723 are fully rohs compliant and halogen-free. features ? halogen-free according to iec 61249-2-21 definition ? 1.8 v to 5.5 v single power supply ? low and flat switch on resistance, 2.5 ? /typ. ? low leakage and parasitic capacitance ? 366 mhz, - 3 db bandwidth ? latch-up current > 300 ma (jesd78) ? space saving packages 2 mm x 2 mm tdfn8 msop8 ? over voltage tolerant ttl/cmos compatible ? compliant to rohs directive 2002/95/ec applications ? healthcare and medical devices ? test instruments ? portable meters ? data acquisitions ? control and automation ? pdas and modems ? communication systems ? audio, video systems ? mechanical reed relay replacement functional block diagram and pin configuration dg721, tdfn-8 no 1 v+ com 1 in 1 in 2 com 2 gnd no 2 1 2 3 4 8 7 6 5 top view adx no 2 com 2 in 1 v+ no 1 com 1 in 2 gnd 8 7 6 5 1 2 3 4 bottom view device marking for msop-8: 721 dg721, msop-8 no 1 v+ com 1 in 1 in 2 com 2 o n d n g 2 1 2 3 4 8 7 6 5 top view pin 1 device marking for tdfn-8: for dg721 x = date/lot traceability code
www.vishay.com 2 document number: 66586 s11-1474-rev. e, 01-aug-11 vishay siliconix dg721, dg722, dg723 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum curr ent ratings. b. all leads welded or soldered to pc board. c. derate 4 mw/c above 70 c. d. derate 10.53 mw/c above 70 c. dg722, tdfn-8 nc 1 v+ com 1 in 1 in 2 com 2 gnd nc 2 1 2 3 4 8 7 6 5 top view pin 1 aex nc 2 com 2 in 1 v+ nc 1 com 1 in 2 gnd 8 7 6 5 1 2 3 4 bottom view device marking for msop-8: 722 dg722, msop-8 nc 1 v+ com 1 in 1 in 2 com 2 c n d n g 2 1 2 3 4 8 7 6 5 top view device marking for tdfn-8: for dg722 x = date/lot traceability code dg723, tdfn-8 no 1 v+ com 1 in 1 in 2 com 2 gnd nc 2 1 2 3 4 8 7 6 5 top view pin 1 device marking for tdfn-8: for dg723 x = date/lot traceability code afx nc 2 com 2 in 1 v+ no 1 com 1 in 2 gnd 8 7 6 5 1 2 3 4 bottom view device marking for msop-8: 723 dg723, msop-8 no 1 v+ com 1 in 1 in 2 com 2 c n d n g 2 1 2 3 4 8 7 6 5 top view truth table (dg721, dg722) logic dg721 dg722 switches 01off 10on truth table (dg723) logic switch-1 switch-2 0offon 1onoff ordering information temperature range package part number - 40 c to 85 c msop-8 dg721dq-t1-ge3 dg722dq-t1-ge3 dg723dq-t1-ge3 tdfn-8 dg721dn-t1-ge4 dg722dn-t1-ge4 DG723DN-T1-GE4 absolute maximum ratings parameter limit unit referenced v+ to gnd - 0.3 to 6 v in, com, nc, no a - 0.3 to (v+ + 0.3) continuous current (any terminal) 50 ma peak current (pulsed at 1 ms, 10 % duty cycle) 200 storage temperature (d suffix) - 65 to 150 c power dissipation (packages) b msop-8 c 320 mw tdfn-8 d 842
document number: 66586 s11-1474-rev. e, 01-aug-11 www.vishay.com 3 vishay siliconix dg721, dg722, dg723 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 specifications (v+ = 3 v) parameter symbol test conditions otherwise unless specified v+ = 3 v, 10 %, v in = 0.4 or 1.5 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc v com full 0 v+ v on-resistance r on v+ = 2.7 v, v com = 0 v to v+, i no , i nc = - 10 ma room full 6.5 10 ? r on flatness d r on flatness v+ = 2.7 v, v com = 1.1 v to 1.6 v, i no , i nc = - 10 ma room 0.4 r on match d r on match v+ = 2.7 v, v d = 1.1 v to 1.6 v, i d = - 10 ma room full 0.3 0.9 switch off leakage current i no(off) i nc(off) v+ = 3.3 v v no , v nc = 1 v/3 v, v com = 3 v/1 v room full - 0.25 - 0.35 0.25 0.35 na i com(off) room full - 0.25 - 0.35 0.25 0.35 channel-on leakage current i com(on) v+ = 3.3 v, v no , v nc = v com = 1 v/3 v room full - 0.25 - 0.35 0.25 0.35 digital control input high voltage v inh full 2 v input low voltage v inl full 0.4 input capacitance d c in f = 1 mhz full 2.4 pf input current i inl or i inh v in = 0 or v+ full - 1 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 2 v, r l = 300 ? , c l = 35 pf figures 1 and 2 room full 16 55 ns turn-off time t off room full 7 40 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? , figure 3 room 1.8 pc bandwidth d bw v+ = 3 v, r l = 50 ? , c l = 5 pf, - 3db room 319 mhz off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 67 db crosstalk d x ta l k room - 92 off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 10 mhz room - 47 crosstalk d x ta l k room - 90 source-off capacitance d c nc/no(off) v in = 0 or v+, f = 1 mhz room 8 pf drain-off capacitance d c com(off) room 9 channel-on capacitance d c on room 22 power supply power supply current i+ v in = 0 or v+, v+ = 3.3 v 1a
www.vishay.com 4 document number: 66586 s11-1474-rev. e, 01-aug-11 vishay siliconix dg721, dg722, dg723 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as determined by the operating suffix. b. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guarantee by design, nor s ubjected to production test. e. v in = input voltage to perform proper function. f. not production tested. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (v+ = 5 v) parameter symbol test conditions otherwise unless specified v+ = 5 v, 10 %, v in = 0.8 or 2.4 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc v com full 0 v+ v on-resistance r on v+ = 4.5 v, v com = 0 v to v+, i no , i nc = 10 ma room full 2.5 4.5 5 ? r on flatness d r on flatness v+ = 4.5 v, v com = 1.3 v to 3 v, i no , i nc = 10 ma room 0.75 1.5 r on match d r on match v+ = 4.5 v, i d = 10 ma, v com = 1.3 v to 3 v room 0.2 0.9 switch off leakage current i no(off) i nc(off) v+ = 5.5 v v no , v nc = 1 v/4.5 v, v com = 4.5 v/1 v room full - 0.25 - 0.35 0.25 0.35 na i com(off) room full - 0.25 - 0.35 0.25 0.35 channel-on leakage current i com(on) v+ = 5.5 v v no , v nc = v com = 1 v/4.5 v room full - 0.25 - 0.35 0.25 0.35 digital control input high voltage v inh full 2.4 v input low voltage v inl full 0.8 input capacitance c in f = 1 mhz full 2.2 pf input current i inl or i inh v in = 0 or v+ full - 0.1 0.005 0.1 a dynamic characteristics tu r n - o n t i m e d t on v no or v nc = 3 v, r l = 300 ? , c l = 35 pf figures 1 and 2 room full 17 30 40 ns turn-off time d t off room full 9 35 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? , figure 3 room 2.2 pc bandwidth d bw v+ = 5 v, r l = 50 ? , c l = 5 pf, - 3 db room 366 mhz off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 67 db crosstalk d x ta l k room - 90 off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 10 mhz room - 47 crosstalk d x ta l k room - 90 source-off capacitance d c nc/no(off) v in = 0 or v+, f = 1 mhz room 8 pf drain-off capacitance d c com(off) room 9 channel-on capacitance d c on room 22 power supply power supply range v+ 2.6 4.3 v power supply current i+ v in = 0 or v+, v+ = 5.5 v full 2a
document number: 66586 s11-1474-rev. e, 01-aug-11 www.vishay.com 5 vishay siliconix dg721, dg722, dg723 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) r on vs. v d and single supply voltage r on vs. analog voltage and temperature leakage current vs. temperature v d - analog v oltage ( v ) r o n - on-resistance ( ) 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 t = 25 c i n o/ n c = - 10 ma v + = 1. 8 v v + = 2.4 v v + = 2.7 v v + = 3.0 v v + = 3.3 v v + = 4.5 v v + = 5.0 v v + = 5.5 v v d - analog v oltage ( v ) r o n - on-resistance ( ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v + = 4.5 v i n o/ n c = - 10 ma - 40 c + 25 c + 8 5 c temperat u re (c) leakage c u rrent (pa) 0.1 1 10 100 - 60 - 40 - 20 0 20 40 60 8 0 100 120 v + = 5.5 v com(o n ) i i com(off) i n o(off) r on vs. analog voltage and temperature supply current vs. input switching frequency switching threshold vs. supply voltage v d - analog v oltage ( v ) r o n - on-resistance ( ) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8 .0 8 .5 9.0 9.5 10 0 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 1.6 1. 8 2.0 2.2 2.4 2.6 2. 8 v + = 2.7 v i n o/ n c = - 10 ma - 40 c + 25 c + 8 5 c inp u t s w itching fre qu ency (hz) i+ - s u pply c u rrent (a) 10 ma 1 ma 100 a 10 a 1 a 100 na 10 na 1 na 100 pa 10 100 1 k 10 k 100 k 1 m 10 m v + = 1. 8 v v + = 3.0 v v + = 3.3 v v + = 5.0 v v + = 5.5 v v + - s u pply v oltage ( v ) v t - s w itching threshold ( v ) 0.5 0.6 0.7 0. 8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1. 8 1.9 2.0 2.1 2.2 1.5 2.0 2.5 3.0 3. 5 4.0 4.5 5.0 5.5 v il v ih
www.vishay.com 6 document number: 66586 s11-1474-rev. e, 01-aug-11 vishay siliconix dg721, dg722, dg723 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) test circuits insertion loss vs. frequency crosstalk vs. frequency - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 fre qu ency (mhz) loss (db) 1 10 100 1000 10 000 - 100 - 90 - 8 0 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 fre qu ency (mhz) crosstalk (db) 1 10 100 1000 off isolation vs. frequency charge injection vs. analog voltage - 100 - 90 - 8 0 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 fre qu ency (mhz) off isolation (db) 1 10 100 1000 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 0123456 charge (pc) source volts v+ = 2.7 v v+ = 3 v v+ = 4.5 v v+ = 5.5 v c l = 1 nf figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 v out gnd v+ 50 % 0 v logic input switch output t on t off logic "1" = switch on logic input waveforms inverted for switches that have the opposite logic sense. switch output 0.9 x v ou t t r < 5 ns t f < 5 ns v inh v inl v out =v com r l r l +r on
document number: 66586 s11-1474-rev. e, 01-aug-11 www.vishay.com 7 vishay siliconix dg721, dg722, dg723 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?66586 . figure 2. charge injection off on on in v out v out q = v out x c l c l = 1 nf com r gen v out nc or no v in = 0 - v+ in v gen gnd v+ v+ in depends on switch configuration: input polarity determined by sense of switch. + figure 3. off-isolation in gnd nc or no 0 v, 2.4 v 10 nf com off isolation = 20 log v com v no/ nc r l analyzer v+ v+ figure 4. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+ figure 5. channel to channel crosstalk r l 10 nf com 2 r l n o 2 com 1 n c 1 analyzer v i n 1 v i n 2 g n d v + v +
document number: 67493 www.vishay.com revison: 07-feb-11 1 package information vishay siliconix case outline for tdfn8 2 x 2 note 1. all dimensions are in millimeters which will govern. 2. max. package wa rpage is 0.05 mm. 3. max. allowable burrs is 0. 076 mm in all directions. 4. pin #1 id on top will be laser/ink marked. 5. dimension applies to meatlized termin al and is measured between 0.20 mm and 0. 25 mm from terminal tip. 6. applied only for terminals. 7. applied for expose d pad and terminals. top vie w side vie w bottom vie w k k l d2 pin 1 indicator (optional) 8 7 6 5 1 2 3 4 b 5 e e2 1 2 3 4 8 7 6 5 d e a a3 a1 7 6 0.05 c index area (d/2 x e/2) millimeters inches dim. min. nom. max. min. nom. max. a 0.50 0.55 0.60 0.020 0.022 0.024 a1 0.00 - 0.05 0.000 - 0.002 a3 0.152 ref 0.006 ref b 0.18 0.23 0.28 0.007 0.009 0.011 d 1.95 2.00 2.05 0.077 0.079 0.081 d2 0.75 0.80 0.85 0.030 0.031 0.033 e 0.50 bsc 0.020 bsc e 1.95 2.00 2.05 0.077 0.079 0.081 e2 1.40 1.45 1.50 0.055 0.057 0.059 k - 0.20 - - 0.008 - l 0.30 0.35 0.40 0.012 0.014 0.016 ecn: c11-0033 rev. a, 07-feb-11 dwg: 5997
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 71244 12-jul-02 www.vishay.com 1 msop: 8?leads jedec part number: mo-187, (variation aa and ba) n = 8l millimeters dim min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.25 - 0.38 8 b 1 0.25 0.30 0.33 8 c 0.13 - 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.65 bsc e 1 1.95 bsc l 0.40 0.55 0.70 4 n 8 5 0 4 6 ecn: t-02080?rev. c, 15-jul-02 dwg: 5867
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.
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